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APDS-9250 digital rgb, ir and ambient light sensor data sheet description the APDS-9250 device uses 4 individual channels of red, green, blue, and ir (rgb+ir) in a specially designed matrix arrangement. this allows the device to have optimal angular response and accurate rgb spectral response with high lux accuracy over various light sources. APDS-9250 supports the i 2 c interface and has a program - mable interrupt controller that frees up micro-controller resources. the device detects light intensity under a variety of lighting conditions and through a variety of attenua - tion materials, including dark glass. APDS-9250 could be confgured as ambient light sensor and rgb+ir sensor. the color-sensing feature is useful in applications such as led rgb backlight control, solid-state lighting, refected led color sampler, or fuorescent light color temperature detection. the integrated ir blocking flter makes this device an excellent ambient light sensor and color tem - perature monitor sensor together with the temperature compensation that allows output to have less variation over the temperature. ordering information part number packaging quantity APDS-9250 tape & reel 5000 per reel features ? colour and ambient light sensing (cs-rgb and als) - accuracy of correlated color temperature (cct) - individual channels for red, green, blue and infared - approximates human eye response with green channel - red, green, blue, infrared and als sensing - high sensitivity in low lux condition C ideally suited for operation behind dark glass - wide dynamic range: 18,000,000: 1 - up to 20-bit resolution ? power management - low active current C 130 a typical - low standby current C 1a typical ? i 2 c-bus fast mode compatible interface - up to 400 khz (i 2 c fast-mode) - dedicated interrupt pin ? small package l 2.0 w 2.0 h 0.65 mm applications ? oled display control ? rgb led backlight control ? ambient light color temperature sensing
2 functional block diagram i/o pins confguration pin name type description 1 scl i i 2 c serial clock input terminal C clock signal for i 2 c serial data 2 sda i/o serial data i/o for i 2 c 3 vdd supply power supply voltage 4 int o interrupt C open drain 5 nc no connect 6 gnd ground power supply ground. all voltages are referenced to gnd description: the APDS-9250 device contains multiple photodiodes for light sensor (r, g, b, ir channel) that are designed in a matrix placement to achieve optimal angular response at the fall of incident light angle. the device provides on-chip multiple diodes, adcs, state machine, non-volatile memory and an i 2 c interface. integration of all color sensing channels occurs simulta - neously. upon completion of the conversion cycle, the conversion result is transferred to the corresponding data registers. communication with the device is accomplished through a fast (up to 400 khz), two-wire i 2 c serial bus for easy connection to a microcontroller or embedded con - troller. the APDS-9250 provides a separate pin for inter - rupts. when interrupts are enabled and a preset value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling frmware. the interrupt feature simplifes and improves system ef - ciency by eliminating the need to poll a sensor for a light intensity. an interrupt is generated after completion of new conversion of the light sensor channels where the light sensor interrupt source can work on any of the red, green, blue, ir channels. additionally, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. rgb + ir control red adc/data green adc/data blue adc/data ir adc/data upper threshold lower threshold interrupt i2c interfacing int scl sda vdd gnd
3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)? parameter symbol min. max. units conditions power supply voltage [1] v dd 3.8 v max voltage on scl, sda, int pads v i2c -0.5 3.8 v storage temperature range t stg ?40 85 c ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may afect device reliability. note 1. all voltages are with respect to gnd. recommended operating conditions parameter symbol min. typ. max. units operating ambient temperature t a -40 85 c supply voltage v dd 1.7 3.6 v supply voltage accuracy, v dd total error including transients -3 3 % operating characteristics, v dd = 2.8 v, t a = 25c (unless otherwise noted) parameter symbol min typ max units test conditions active mode current i cs 130 a v dd =2.8v, gain mode 3 standby current i stby 1 2 a in standby mode. no active i 2 c communication scl, sda input high voltage v ih 1.5 v dd v scl, sda input low voltage v il 0 0.4 v v ol int, output low voltage v ol 0 0.4 v i leak leakage current, sda, scl, int pins i leak -5 5 a optical characteristics, v dd = 2.8 v, t a = 25c (unless otherwise noted) parameter test condition red channel green channel blue channel ir channel unit min. max. min. max. min. max. min. max. irradiance response = 465 0 5 6 17 80 120 0 4 % = 525 3 10 80 120 10 30 0 3 = 625 80 120 18 33 0 3 0 3 = 850 0 3 0 3 0 3 80 120 notes: 1. the percentage shown represents the ratio of the respective red, green, or blue channel value to the ir channel value. 2. the 465 nm input irradiance is supplied by an ingan light-emitting diode with the following characteristics: dominant wavelength _d = 465 nm, spectral halfwidth __? = 22 nm. 3. the 525 nm input irradiance is supplied by an ingan light-emitting diode with the following characteristics: dominant wavelength _d = 525 nm, spectral halfwidth __? = 35 nm. 4. the 625 nm input irradiance is supplied by a alingap light-emitting diode with the following characteristics: dominant wavelength _d = 625 nm, spectral halfwidth __? = 15 nm. 5. the 850 nm input irradiance is supplied by a alingap light-emitting diode with the following characteristics: dominant wavelength _d = 850 nm, spectral halfwidth __? = 40 nm. rgb characteristics, v dd = 2.8 v, t a = 25c (unless otherwise noted) parameter min. typ. max. units test conditions dark count 0 3 counts adc integration time 2.97 3.125 3.28 ms full scale adc counts per step 8192 counts 13 bit full scale adc count value 262,143 counts 18 bit, 100ms, g=1x
4 als characteristics, v dd = 2.8 v, t a = 25c (unless otherwise noted) parameter symbol min typ max units test conditions peak wavelength p 550 nm min integration time t intmin1 3.125 ms t intmin2 50 ms with 50/60hz rejection max integration time t intmax 400 ms with 50/60hz rejection output resolution res als 13 18 20 bit programmable adc count value 1000 count = 530nm, 50ms, gain=3x, ee=59uw/cm 2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 normalized responsivity angular displacement (degree) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 300 400 500 600 700 800 900 1000 1100 relative response wavelength (nm) red green blue ir 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 avg sensor lux meter lux 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 avg sensor lux meter lux figure 1. normalized als pd angular response figure 2. normalized pd spectral response figure 3. als sensor lux vs meter lux using white light figure 4. als sensor lux vs meter lux using white light
5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -60 -40 -20 0 20 40 60 80 100 normalized idd @ 2.8v, 25c temperature (c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 normalized idd @ 2.8v , 25c v dd (v) 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 avg sensor lux meter lux 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 -60 -40 -20 0 20 40 60 80 100 relative deviation temperature (c) gain 1x gain 3x gain 6x gain 9x gain 18x figure 6. normalized idd vs vdd figure 7. normalized idd vs temperature figure 5. als sensor lux vs meter lux using incandescent light figure 8. als vs temperature @ 1000 lux (white led)
6 light sensor operation light sensor (ls) measurements can be activated by setting the ls_en bit to 1 in the main_ctrl register. in light sensor mode the user can select to activate either als or cs operation mode. als mode is activated by setting cs_mode bit to 0 while cs mode is activated by cs_mode bit set to 1 in the main_ctrl register. as soon as light sensor become activated through i2c command, the internal support blocks are powered on. once the voltages and currents are settled (typically after 5ms), the state machine checks for trigger events from a measurement scheduler to start the ls conversions according to the selected measurement repeat rates. once ls_en is changed back to 0, a conversion running on the respective sensor will be completed and the relevant adcs and support blocks will move to standby mode thereafter. light sensor interrupt the ls interrupt is enabled by ls_int_en=1. it can function as either threshold triggered (ls_var_mode=0) or variance trigged (ls_var_mode=1). the ls interrupt source generator can work on any of the four ls channels (r, g, b, ir). the ls interrupt source is selected by the ls_ int_sel bits in the int_cfg register. the light sensor threshold interrupt is enabled with ls_int_en = 1 and ls_var_mode = 0. it is set when the data of the selected ls_data input register (ls_red, ls_green, ls_blue, ls_ir) is above the upper or below the lower threshold for a specifed number of consecutive measurements. the light sensor variance interrupt is enabled with ls_ int_en = 1 and ls_var_mode = 1. it is set when the absolute value of the diference between the previous and current ls_data data value is above the decoded ls variance threshold for a specifed number of consecutive measurements. i2c protocol interface and control of the APDS-9250 is accomplished through an i 2 c serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. the device supports a single slave address of 0x52 hex using 7 bit addressing protocol. (contact factory for other addressing options.) start nvm read idle wait for osc power up check cs do cs conversion do als conversion ls_en==0 ls_en==1 cs_mode==0 ls_en==1 cs_mode==1 system state machine start up after power-on or software reset the main state machine is set to start state during power-on or software reset. as soon as the reset is released, the internal oscillator is started and the programmed i2c address and the trim values are read from the internal non volatile memory (nvm) trimming data block. the device enters standby mode as soon as the idle state is reached. note: as long as the i2c address has not yet been read, the device will respond with nack to any i2c command and ignore any request to avoid responding to a wrong i2c address. standby mode standby mode is the default mode after power-up. in this state, the oscillator, all internal support blocks, and the adcs are switched of but i2c communication is fully supported.
7 i 2 c register read timing diagram i 2 c register write timing diagram r e gi s t e r r e ad (i 2 c tm r e ad ) s sla v e a d d r 7 b it 0 a a d d r e s s 8 b it a s sla v e a d d r 7 b it 1 a d a t a 8 b it n p s sla v e a d d r 7 b it 0 a a d d r e s s 8 b it a s sla v e a d d r 7 b it 1 a d a t a 8 - b it a d a t a 8 - b i t a ? d a t a 8 - b i t n p fr o m m as t e r t o sl a v e fr o m sl a v e t o m as t e r s p a n st ar t c o n d ito n st o p c o n d ito n a c k n o w l e d g e ( a c k) n o t a c k n o w l e d g e ( n a c k) r e ad w r it e r e ad w r it e r e gi s t e r b l o c k r e ad (i 2 c tm r e ad ) s sla v e a d d r 7 b it 0 a a d d r e s s a d a t a 8 - b it a p s sla v e a d d r 7 b it 0 a a d d r e s s a d a t a 8 - b it a d a t a 8 - b it a ? d a t a 8 - b it a p w r it e w r it e r e gi s t e r w r i t e (i 2 c tm w r i t e ) fr o m m as t e r t o sl a v e fr o m sl a v e t o m as t e r s p a n st ar t c o n d ito n st o p c o n d ito n a c k n o w l e d g e ( a c k) n o t a c k n o w l e d g e ( n a c k) r e gi s t e r block w r i t e (i 2 c tm w r i t e ) i2c register write the device registers can be written to individually or in block write mode. when two or more bytes are written in block write mode, reserved registers and read-only registers are skipped. the transmitted data is automati - cally applied to the next writable register. if a register includes read (r) and read/write (rw) bits, the register is not skipped. data written to read-only bits are ignored. if the last valid address of the device address range is reached but the master attempts to continue the block write operation, the address counter of the device will not roll over. the device will return nack for every following byte sent by the master until the i 2 c? operation is ended. if a write access is started on an address belonging to a non-writeable register, the device will return nack until the i 2 c? operation is ended. write operations must follow the timing diagram shown below. i2c register read the registers can be read individually or in block read mode. when two or more bytes are read in block read mode, reserved register addresses are skipped and the next valid address is referenced. if the last valid address has been reached, but the master continues with the block read, the address counter in the device will not roll over and the device returns 00hex for every subsequent byte read. the block read operation is the only way to ensure correct data read out of multi-byte registers and to avoid splitting of results with high and low bytes originating from diferent conversions. during block read access on ls and ps result registers, the result update is blocked. if a read access is started on an address belonging to a non-readable register, the device will return nack until the i 2 c? operation is ended. read operations must follow the timing diagram shown below.
8 i 2 c interface C bus timing sda scl t low t hdsta t bus t hdsta t sudat t susto t susta t high t hddat bus timing characteristics parameter symbol standard mode fast mode units maximum scl clock frequency f scl 100 400 khz minimum start condition hold time relative to scl edge t dsta 4 s minimum scl clock low width t low 4.7 s minimum scl clock high width t high 4 s minimum start condition setup time relative to scl edge t susta 4.7 s minimum data hold time on sda relative to scl edge t hddat 0 s minimum data setup time on sda relative to scl edge t sudat 0.1 0.1 s minimum stop condition setup time on scl t susto 4 s minimum bus free time between stope condition and start condition t bus 4.7 s
9 register set: the APDS-9250 is controlled and monitored by data registers and a command register accessed through the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. address type name description reset value 00hex rw main_ctrl ls operation mode control, sw reset 00hex 04hex rw ls_meas_rate ls measurement rate and resolution in active mode 22hex 05hex rw ls_gain ls analog gain range 01hex 06hex r part_id part number id and revision id b2hex 07hex r main_status power-on status, interrupt status, data status 20hex 0ahex r ls_data_ir_0 ir adc measurement data - lsb 00hex 0bhex r ls_data_ir_1 ir adc measurement data 00hex 0chex r ls_data_ir_2 ir adc measurement data - msb 00hex 0dhex r ls_data_green_0 green adc measurement data - lsb 00hex 0ehex r ls_data_green_1 green adc measurement data 00hex 0fhex r ls_data_green_2 green adc measurement data - msb 00hex 10hex r ls_data_blue_0 blue adc measurement data - lsb 00hex 11hex r ls_data_blue_1 blue adc measurement data 00hex 12hex r ls_data_blue_2 blue adc measurement data - msb 00hex 13hex r ls_data_red_0 red adc measurement data - lsb 00hex 14hex r ls_data_red_1 red adc measurement data 00hex 15hex r ls_data_red_2 red adc measurement data - msb 00hex 19hex rw int_cfg interrupt confguration 10hex 1ahex rw int_persistence interrupt persist setting 00hex 21hex rw ls_thres_up_0 ls interrupt upper threshold, lsb ffhex 22hex rw ls_thres_up_1 ls interrupt upper threshold ffhex 23hex rw ls_thres_up_2 ls interrupt upper threshold, msb 0fhex 24hex rw ls_thres_low_0 ls interrupt lower threshold, lsb 00hex 25hex rw ls_thres_low_1 ls interrupt lower threshold 00hex 26hex rw ls_thres_low_2 ls interrupt lower threshold, msb 00hex 27hex rw ls_thres_var ls interrupt variance threshold 00hex
10 main_ctrl default value : 00hex 7 6 5 4 3 2 1 0 0 0 0 sw_reset 0 cs_mode ls_en 0 0x00 field bit description sw_reset 4 1 = reset will be triggered cs_mode 2 0 = als, ir and compensation channels activated 1 = all rgb+ir + compensation channels activated ls_en 1 1 = light sensor active 0 = light sensor standby writing to this register stops the ongoing measurements and starts new measurements (depends on the enable bit). ls_meas_rate default value : 22hex 7 6 5 4 3 2 1 0 0 ls resolution/bit width 0 ls measurement rate 0x04 field bit description ls resolution/bit width 6:4 000 : 20 bit C 400ms 001 : 19 bit C 200ms 010 : 18 bit C 100ms (default) 011 : 17 bit C 50ms 100 : 16 bit C 25ms 101 : 13 bit C 3.125ms 110 : reserved 111 : reserved ls measurement rate 2:0 000 C 25ms 001 C 50ms 010 C 100ms (default) 011 C 200ms 100 C 500ms 101 C 1000ms 110 C 2000ms 111 C 2000ms when the measurement repeat rate is programmed to be faster than possible for the specifed adc measurement time, the repeat rate will be lower than programmed (maximum speed). writing to this register stops the ongoing measurement and starts new measurements (depending on the respective bits)
11 ls_gain default value : 01hex 7 6 5 4 3 2 1 0 0 0 0 0 0 gain range 0x05 field bit description gain range 2:0 000 : gain 1 001 : gain 3 010 : gain 6 011 : gain 9 100 : gain 18 the channels of the light sensor always run on the same gain range setting. sensitivity settings correlate between the channels. result output in lux is available from als/green channel. writing to this register stops the ongoing measurement and starts new measurements (depending on the respective bits) part_id default value : b2hex 7 6 5 4 3 2 1 0 part id revision id 0x06 field bit description part number id 7:4 part number id revision id 3:0 revision id of the component. main_status default value : 20hex 7 6 5 4 3 2 1 0 0 0 power on status ls interrupt status ls data status 0 0 0 0x07 field bit description power on status 5 1 = part went through a power-up event, either because the part was turned on or because there was power supply disturbance. all interrupt threshold settings in the registers have been reset to power-on default states and should be examined if necessary. the fag is cleared after the register is read. ls interrupt status 4 0 : interrupt condition not fulflled (default) 1 : interrupt condition fulflled (cleared after read) ls data status 3 0 : old data, already read (default) 1 : new data, not yet read (cleared after read)
12 ls_data_ir default value : 00hex, 00hex, 00hex 7 6 5 4 3 2 1 0 ls_data_ir_0 [7:0] 0x0a ls_data_ir_1 [15:8] 0x0b 0 0 0 0 ls_data_ir_2 [19:16] 0x0c ir channel output data (unsigned integer, 13 to 20 bit, lsb aligned) the ir channel output is already temperature compensated internally: ls_data_ir C (irint C ls_data_comp) when an i2c? read operation is active and points to an address in the range 07hex to 18hex, all registers in this range are locked until the i2c? read operation is completed or this address range is left. this guarantees that the data in the registers comes from the same measurement even if an additional measurement cycle ends during the read operation. new measurement data is stored into temporary registers and the actual ls_data registers are updated as soon as there is no on-going i2c? read operation to the address range 07hex to 18hex. reg 0ahex bit[7:0] ir diode data least signifcant data byte reg 0bhex bit[7:0] ir diode data intervening data byte reg 0chex bit[3:0] ir diode data most signifcant data byte ls_data_green default value : 00hex, 00hex, 00hex 7 6 5 4 3 2 1 0 ls_data_green_0 [7:0] 0x0d ls_data_green_1 [15:8] 0x0e 0 0 0 0 ls_data_green_2 [19:16] 0x0f als/cs green channel digital output data. the channel output is already temperature compensated internally: ls_data_green = (greenint C ls_data_comp) when an i2c? read operation is active and points to an address in the range 07hex to 18hex, all registers in this range are locked until the i2c? read operation is completed or this address range is left. this guarantees that the data in the registers comes from the same measurement even if an additional measurement cycle ends during the read operation. new measurement data is stored into temporary registers and the actual ls_data registers are updated as soon as there is no on-going i2c? read operation to the address range 07hex to 18hex. reg 0dhex bit[7:0] als / green diode data least signifcant data byte reg 0ehex bit[7:0] als / green diode data intervening data byte reg 0fhex bit[3:0] als / green diode data most signifcant data byte
13 ls_data_blue default value : 00hex, 00hex, 00hex 7 6 5 4 3 2 1 0 ls_data_blue_0 [7:0] 0x10 ls_data_blue_1 [15:8] 0x11 0 0 0 0 ls_data_blue_2 [19:16] 0x12 cs blue channel output data. the channel output is already temperature compensated internally: ls_data_blue = (blueint C ls_data_comp) when an i2c? read operation is active and points to an address in the range 07hex to 18hex, all registers in this range are locked until the i2c? read operation is completed or this address range is left. this guarantees that the data in the registers comes from the same measurement even if an additional measurement cycle ends during the read operation. new measurement data is stored into temporary registers and the actual ls_data registers are updated as soon as there is no on-going i2c? read operation to the address range 07hex to 18hex. reg 10hex bit[7:0] blue diode data least signifcant data byte reg 11hex bit[7:0] blue diode data intervening data byte reg 12hex bit[3:0] blue diode data most signifcant data byte ls_data_red default value : 00hex, 00hex, 00hex 7 6 5 4 3 2 1 0 ls_data_red_0 [7:0] 0x13 ls_data_red_1 [15:8] 0x14 0 0 0 0 ls_data_red_2 [19:16] 0x15 the channel output is already temperature compensated internally: ls_data_red = (redint C ls_data_comp) when an i2c? read operation is active and points to an address in the range 07hex to 18hex, all registers in this range are locked until the i2c? read operation is completed or this address range is left. this guarantees that the data in the registers comes from the same measurement even if an additional measurement cycle ends during the read operation. new measurement data is stored into temporary registers and the actual ls_data registers are updated as soon as there is no on-going i2c? read operation to the address range 07hex to 18hex. reg 13hex bit[7:0] red diode data least signifcant data byte reg 14hex bit[7:0] red diode data intervening data byte reg 15hex bit[3:0] red diode data most signifcant data byte
14 int_cfg default value : 10hex 7 6 5 4 3 2 1 0 0 0 ls interrupt source ls variation int mode ls interrupt enable 0 0 0x19 0 0 ls_int_sel ls_var_mode ls_int_en 0 0 field bit description ls_int_sel 5:4 00 : ir channel 01 : als/green channel (default) 10 : red channel 11 : blue channel ls_var_mode 3 0 : ls threshold interrupt mode (default) 1 : ls variation interrupt mode ls_int_en 2 0 : ls interrupt disabled (default) 1 : ls interrupt enabled int_persistence default value : 00hex 7 6 5 4 3 2 1 0 ls_persist 0 0 0 0 0x1a this register sets the number of similar consecutive ls interrupt events that must occur before the interrupt is asserted. field bit description ls_persist 7:4 0000 : every ls value out of threshold range (default) asserts an interrupt 0001 : 2 consecutive ls values out of threshold range assert an interrupt 1111 : 16 consecutive ls values out of threshold range assert an interrupt
15 ls_thres_up default value : ffhex, ffhex, 0fhex 7 6 5 4 3 2 1 0 ls_thres_up_0 [7:0] 0x21 ls_thres_up_1 [15:8] 0x22 0 0 0 0 ls_thres_up_2 [19:16] 0x23 ls_thres_up sets the upper threshold value for the ls interrupt. the interrupt controller compares the value in ls_ thres_up against measured data in the ls_data registers of the selected ls interrupt channel. it generates an interrupt event if data exceeds the threshold level. the data format for ls_thres_up must match that of the ls_data registers. reg 21hex bit[7:0] ls upper interrupt threshold value, lsb reg 22hex bit[7:0] ls upper interrupt threshold value, intervening byte reg 23hex bit[3:0] ls upper interrupt threshold value, msb ls_thres_low default value: 00hex, 00hex, 00hex 7 6 5 4 3 2 1 0 ls_thres_low_0 [7:0] 0x24 ls_thres_low_1 [15:8] 0x25 0 0 0 0 ls_thres_low_2 [19:16] 0x26 ls_thres_low sets the lower threshold value for the ls interrupt. the interrupt controller compares the value in ls_thres_low against measured data in the ls_data registers of the selected ls interrupt channel. it generates an interrupt event if the ls_data is below the threshold level. the data format for ls_thres_low must match that of the ls_data registers. reg 24hex bit[7:0] ls lower interrupt threshold value, lsb reg 25hex bit[7:0] ls lower interrupt threshold value, intervening byte reg 26hex bit[3:0] ls lower interrupt threshold value, msb ls_thres_var default value : 00hex 7 6 5 4 3 2 1 0 0 0 0 0 0 ls_thres_var 0x27 field bit description ls_thres_var 2:0 000 : new ls_data varies by 8 counts compared to previous result 001 : new ls_data varies by 16 counts compared to previous result 010 : new ls_data varies by 32 counts compared to previous result 011 : new ls_data varies by 64 counts compared to previous result 111 : new ls_data varies by 1024 counts compared to previous result
16 application information hardware the application hardware circuit for using implementing rgb, als and ir solution is simple with the APDS-9250 and is shown in following fgure. the bypass capacitor is placed as close to the device package and is connected directly to the power source and to the ground, as shown in figure below. it allows the ac component of the vdd to pass through to ground. suggested to have bypass capacitor that have low efective series resistance (esr) and low efec tive series in - ductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents caused by internal logic switching. pull-up resistors, rsda and rscl, maintain the sda and scl lines at a high level when the bus is free and ensure the signals are pulled up from a low to a high level within the required rise time. a pull-up resistor, rint, is also required for the interrupt (int), which functions as a wired-and signal in a similar fashion to the scl and sda lines. a typical impedance value of 10 k can be used. for a complete description of i 2 c maxi mum and minimum r1 and r2 values, please review the i 2 c specifcation at http:// www.semiconductors.philips.com. mcu scl sda int APDS-9250 scl sda int vdd vbus r sda r scl r int gnd 1uf
17 package outline dimensions 1 2 3 pinout 1- scl 2- sda 3- vdd 4- int 5- nc 6- gnd (0.103) 2 0.10 2 0.10 ic active area center 0.65 0.10 0.65 0.10 (4x) 0.625 0.100 (6x) 0.300 0.050 (6x) 0.75 0.15 (6x) 4 5 6 4 5 6 3 2 1 c l c l c l c l 0.100 0.050 (6x) dimensions are in mm pcb pad layout 0.900 (x6) 0.400 (x6) (2) (2) 0.650 (x4) 1.300 (x3)
18 reel dimensions tape width t w1 w2 w3 8 mm 3 0.50 8.4 + 1.5 - 0.0 14.4 max 7.9 min 10.9 max 13 0.2 arbor hole w3 w1 ? 180 0.50 diameter 60 0.50 hub dia. access hole access hole t tape start slot t tape start slot access hole measured at outer edge w2 measured at hub measured at hub 20.2 min. ccd/keaco made in malaysia front view back view side view dimensions are in mm tape dimensions 8 + - 0.300 0.100 4 0.10 4 0.10 2 0.050 ? 1.50 0.10 ? 1 0.25 1.75 0.10 3.500 0.050 0.200 0.200 0.830 0.050 2.180 0.050 section a-a scale 10 : 1 5 deg max detail c scale 20 : 1 unit orientation 2.180 0.050 section b-b scale 10 : 1 5 deg max a a b b c
19 moisture proof packaging all APDS-9250 options are shipped in moisture proof package. once opened, moisture absorption begins. this part is compliant to jedec msl 3. recommended storage conditions storage temperature 10 c to 30 c relative humidity below 60% rh time from unsealing to soldering after removal from the bag, the parts should be soldered within seven days if stored at the recommended storage conditions. when mbb (moisture barrier bag) is opened and the parts are exposed to the recommended storage conditions more than seven days the parts must be baked before refow to prevent damage to the parts. baking conditions if the parts are not stored per the recommended storage conditions they must be baked before refow to prevent damage to the parts. package temp. time in reels 60c 48 hours in bulk 100c 4 hours note: baking should only be done once. units in a sealed mositure-proof package package is opened (unsealed) environment less than 30 deg c, and less than 60% rh? package is opened less than 168 hours? perform recommended baking conditions no baking is necessary no yes no yes
20 recommended refow profle process zone symbol ? t maximum ? t/ ? time or duration heat up p1, r1 25 c to 150 c 3 c/s solder paste dry p2, r2 150 c to 200 c 100 s to 180s solder refow p3, r3 p3, r4 200 c to 260 c 260 c to 200 c 3 c/s -6 c/s cool down p4, r5 200 c to 25 c -6 c/s time maintained above liquidus point , 217 c > 217 c 60 s to 120 s peak temperature 260 c C time within 5 c of actual peak temperature > 255 c 20 s to 40 s time 25 c to peak temperature 25 c to 260 c 8 mins time above the liquidus point of solder should be between 60 and 120 seconds. this is to assure proper coalescing of the solder paste into liquid solder and the formation of good solder connections. beyond the recommended dwell time the intermetallic growth within the solder con - nections becomes excessive, resulting in the formation of weak and unreliable connections. the temperature is then rapidly reduced to a point below the solidus temperature of the solder to allow the solder within the connections to freeze solid. process zone p4 is the cool down after solder freeze. the cool down rate, r5, from the liquidus point of the solder to 25 c (77 f) should not exceed 6 c per second maximum. this limitation is necessary to allow the pc board and component pins to change dimensions evenly, putting minimal stresses on the component. it is recommended to perform refow soldering no more than twice. 50 100 150 200 250 300 t-time (seconds) 25 80 120 150 180 200 230 255 0 temperature (c) r1 r2 r3 r4 r5 217 max 260 c p1 heat up p2 solder paste dry p3 solder reflow p4 cool down 60 sec to 120 sec above 217 c the refow profle is a straight-line representation of a nominal temperature profle for a convective refow solder process. the temperature profle is divided into four process zones, each with diferent ? t/ ? time tem - perature change rates or duration. the ? t/ ? time rates or duration are detailed in the above table. the temperatures are measured at the component to printed circuit board connections. in process zone p1, the pc board and component pins are heated to a temperature of 150 c to activate the fux in the solder paste. the temperature ramp up rate, r1, is limited to 3 c per second to allow for even heating of both the pc board and component pins. process zone p2 should be of sufcient time duration (100 to 180 seconds) to dry the solder paste. the temperature is raised to a level just below the liquidus point of the solder. process zone p3 is the solder refow zone. in zone p3, the temperature is quickly raised above the liquidus point of solder to 260 c (500 f) for optimum results. the dwell
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2015 avago technologies. all rights reserved. av02-4733en - november 13, 2015 disclaimer: avagos products and software are not specifcally designed, manufactured or authorized for sale as parts, components or assemblies for the planning, construction, maintenance or direct operation of a nucle - ar facility or for use in medical devices or applications. customer is solely responsible, and waives all rights to make claims against avago or its suppliers, for all loss, damage, expense or liability in connection with such use.

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